Each of the integrated circuit systems, involving the information, the communication, the biomedical and the consumer electronic products, and so forth, is developed towards the single chip system. The embedded memory is an indispensable portion of the single chip system, wherein it is the widest to use the SRAM therein, and the SRAM is applied to the temporary data storage and the data transmission.
The biomedical electronics is a quite popular field nowadays. It is unnecessary for the integrated circuit applied to the biomedical to operate in high speed, but it is necessary to operate for a long time, so that the integrated circuit must possess very low power consumption. Causing the circuit to be operated at the subthreshold voltage region provides an effective method to achieve ultra-low power consumption, but the reliability problem accompanied therewith will arrive. In particular, due to the process, the voltage and the temperature variations in the nanometer manufacturing process, the stability becomes the most important factor in the design consideration.
A technical scheme in the prior art disclosed in U.S. Pat. No. 7,385,840 B2 provides an SRAM cell with independent static noise margin, trip voltage, and read current optimization.
A technical scheme in the prior art is disclosed in Reference 1: J. Chang, J.-J. Kim. S. P. Park, and K. Roy, “A 32 kbit 10T subthreshold SRAM array with bitinterleaving and differential read-scheme in 90 nm CMOS”, IEEE Journal of Solid-state Circuits, vol. 44, no. 2, Feb. 2009, pp. 650-658.
A technical scheme in the prior art is disclosed in Reference 2: Leland Chang, R. K. Montoye, Yutaka Nakamura, Kevin A. Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, and Damir Jamsek, “An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches”, IEEE JSSC, April 2008, pp. 956-963.